The present invention relates to a method of fabricating semiconductor devices which is suited for integrating a vertical power transistor and control devices under optimal conditions for each device structure.
A semiconductor device in which a vertical power MOS transistor, logic and/or small-signal control circuits coexist, has been disclosed in Electronic Design, "Mixed MOS Devices Unite in a Switch Chip that Links Power with Smarts", Feb. 21, 1985, pp. 191-198.
FIG. 1 is a section view of this semiconductor integrated circuit, wherein reference numeral 21 denotes an n.sup.+ -type semiconductor substrate, 122 denotes a p-type epitaxial layer, 23 denotes an n-type epitaxial layer, 24 denotes a vertical power MOSFET, 25 denotes a portion of control devices, 26 denotes an n.sup.+ -type buried layer, and 27 denotes a p.sup.+ -type isolation diffusion layer.
Studying the above prior art, however, the present inventors have found problems as described below.
That is, according to the prior art as shown in FIG. 1, the drain electrode of the power MOSFET 24 is drawn from the underlying n.sup.+ -type substrate 21 via the heavily doped n.sup.+ -type buried layer 26 that is formed deep to penetrate through the p-type epitaxial layer 122. However, since the portion 25 of control devices consisting of CMOS logic circuitry and small-signal circuits, has not been provided with the n.sup.+ -type buried layer, there arise problems as follows:
(1) Collector series resistance increases in the portion of control devices; PA0 (2) Latch-up hardness of CMOS decreases; and PA0 (3) Electric current leaks into the substrate due to the increase of current gain h.sub.FE of a parasitic vertical pnp transistor. PA0 (4) Deep p.sup.+ -type isolation layers 27 are required causing the characteristics of the portion 25 of control devices to be deteriorated.
Further, the n-type epitaxial layer 23 has the same thickness in the vertical device portion where the power MOSFET 24 is formed and in the control device portion 25 where the CMOS logic circuitry and small-signal circuit are formed. Coexistence of the power MOSFET 24 makes the n-type epitaxial layer 23 thick even in the portion 25 of control devices where the n-type epitaxial layer needs not have an increased thickness. Because of this, the following additional problem arises
In order for a power MOSFET 24 to deliver a high current at a low resistance, a deep highly doped n.sup.+ -type penetration layer 26 must be formed to penetrate through the p-type epitaxial layer 22. In forming the p.sup.+ -type isolation diffusion layers 27, furthermore, impurities diffuse up from the n.sup.+ -type penetration layer 26 into the n-type epitaxial layer 23 so that its thickness decreases substantially. Therefore, antimony ions having a small coefficient of diffusion are usually used as impurities for the n.sup.+ -type penetration layer 26. The diffusion must be effected at 1200.degree. C. for as long as 15 hours even when the n.sup.+ -type diffusion layer 26 is to be formed maintaining a thickness of about 7 .mu.m. To form the n.sup.+ -type penetration layer 26 maintaining a thickness of greater than 10 .mu.m, therefore, the diffusion must be carried out at a temperature of as high as 1200.degree. C. for a period of as long as 24 hours or more.
According to the conventional art, as described above, the diffusion must be effected at a high temperature for an extended period of time, resulting in an increase in the manufacturing time and cost. Further, since the n.sup.+ -type penetration layer 26 expands in the lateral direction, an increased area is required. Moreover, crystallinity of the semiconductor (silicon) is disturbed by the heat-treatment that is effected for an extended period of time to form the n.sup.+ -type penetration layer 26, causing the transistor to generate noise and causing the yield to decrease.